Author Topic: Need some help with my libretro port  (Read 47743 times)

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #90 on: October 11, 2016, 05:16:38 PM »
Hi !

I've been working on libretro-fba last few days, and i decided to try fixing those irem games on arm again, and after trying to bprint tons of things inside d_m72.cpp on both my pc and my raspberry i think i've finally got some lead ! Here is my custom m72_main_write :
Code: [Select]
void __fastcall m72_main_write(UINT32 address, UINT8 data)
{
bprintf (PRINT_NORMAL, _T("address %d\n"), address);
if ((address & 0xff000) == 0xb0000) {
bprintf (PRINT_NORMAL, _T("protection_write cond\n"));
protection_write(address, data);
return;
}

if ((address & 0xff000) == 0xc8000) {
bprintf (PRINT_NORMAL, _T("palette_write cond 1\n"));
if (address & 1) data = 0xff;
  DrvPalRAM[(address & 0xdff) | 0x0000] = DrvPalRAM[(address & 0xdff) | 0x0200] = data | 0xe0;
palette_write(address, 0);
return;
}

if ((address & 0xff000) == 0xcc000) {
bprintf (PRINT_NORMAL, _T("palette_write cond 2\n"));
if (address & 1) data = 0xff;
  DrvPalRAM[(address & 0xdff) | 0x1000] = DrvPalRAM[(address & 0xdff) | 0x1200] = data | 0xe0;
palette_write(address, 1);
return;
}
}
I noticed the following output while running rtype :
On x86 (working) :
Code: [Select]
RetroArch [libretro DEBUG] :: address 819200
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819201
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819202
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819203
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819204
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819205
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819206
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819207
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819208
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819209
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819210
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819211
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819212
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819213
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819214
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819215
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819216
RetroArch [libretro DEBUG] :: palette_write cond 1
RetroArch [libretro DEBUG] :: address 819217
...
On ARM (black screen and no sound):
Code: [Select]
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 1
RetroArch [libretro DEBUG] :: address 2
RetroArch [libretro DEBUG] :: address 3
RetroArch [libretro DEBUG] :: address 4
RetroArch [libretro DEBUG] :: address 5
RetroArch [libretro DEBUG] :: address 6
RetroArch [libretro DEBUG] :: address 7
RetroArch [libretro DEBUG] :: address 8
RetroArch [libretro DEBUG] :: address 9
RetroArch [libretro DEBUG] :: address 10
RetroArch [libretro DEBUG] :: address 11
RetroArch [libretro DEBUG] :: address 12
RetroArch [libretro DEBUG] :: address 13
RetroArch [libretro DEBUG] :: address 14
RetroArch [libretro DEBUG] :: address 15
RetroArch [libretro DEBUG] :: address 16
RetroArch [libretro DEBUG] :: address 17
RetroArch [libretro DEBUG] :: address 18
RetroArch [libretro DEBUG] :: address 19
RetroArch [libretro DEBUG] :: address 20
RetroArch [libretro DEBUG] :: address 21
RetroArch [libretro DEBUG] :: address 22
RetroArch [libretro DEBUG] :: address 23
RetroArch [libretro DEBUG] :: address 24
RetroArch [libretro DEBUG] :: address 25
RetroArch [libretro DEBUG] :: address 26
RetroArch [libretro DEBUG] :: address 27
RetroArch [libretro DEBUG] :: address 28
RetroArch [libretro DEBUG] :: address 29
RetroArch [libretro DEBUG] :: address 30
RetroArch [libretro DEBUG] :: address 31
RetroArch [libretro DEBUG] :: address 32
RetroArch [libretro DEBUG] :: address 33
RetroArch [libretro DEBUG] :: address 34
RetroArch [libretro DEBUG] :: address 35
RetroArch [libretro DEBUG] :: address 36
RetroArch [libretro DEBUG] :: address 37
RetroArch [libretro DEBUG] :: address 38
RetroArch [libretro DEBUG] :: address 39
RetroArch [libretro DEBUG] :: address 40
RetroArch [libretro DEBUG] :: address 41
...
The difference seems big enough to be the cause of the whole issue. On ARM it seems very unlikely he would enter any of the conditions in m72_main_write, probably leading to the whole issue. So, after following the track further, i kinda understand there is something wrong happening on ARM in either cpu_writemem20, VezWriteByte, VezWriteWord, VezWriteLong or VezCheatWrite from nec_intf.cpp , but i'm kinda lost at what i should do next to track the issue, do you have any idea ?
« Last Edit: October 12, 2016, 01:43:14 AM by barbudreadmon »

Offline dink

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Re: Need some help with my libretro port
« Reply #91 on: October 11, 2016, 06:40:32 PM »
I'm trying to deduce something. With your debug code, please run Mr.Heli and post what you get.


Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #92 on: October 12, 2016, 01:48:36 AM »
I edited my last post, some of my output was from another of my bprints, things will be more clear now.
mrheli on x86 (working) :
Code: [Select]
RetroArch [libretro DEBUG] :: address 720896
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720897
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720898
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720899
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720900
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720901
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720902
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720903
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720904
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720905
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720906
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720907
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720908
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720909
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720910
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720911
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720912
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720913
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720914
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720915
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720916
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720917
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720918
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720919
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720920
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720921
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720922
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720923
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720924
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720925
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720926
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720927
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720928
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720929
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720930
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720931
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720932
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720933
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720934
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720935
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720936
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720937
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720938
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720939
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720940
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720941
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720942
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720943
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720944
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720945
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720946
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720947
RetroArch [libretro DEBUG] :: protection_write cond
RetroArch [libretro DEBUG] :: address 720948
RetroArch [libretro DEBUG] :: protection_write cond
...
on ARM (black screen and no sound) :
Code: [Select]
RetroArch [libretro DEBUG] :: address 3
RetroArch [libretro DEBUG] :: address 2
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
RetroArch [libretro DEBUG] :: address 0
...
« Last Edit: October 12, 2016, 01:51:24 AM by barbudreadmon »

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #93 on: October 13, 2016, 01:55:20 AM »
It seems there is nothing wrong in cpu_writemem20, VezWriteByte, VezWriteWord, VezWriteLong or VezCheatWrite.

I added the following :
Code: [Select]


void cpu_writemem20(UINT32 a, UINT8 d)
{
bprintf (PRINT_NORMAL, _T("cpu_writemem20 %d\n"), a);
a &= 0xFFFFF;

UINT8 * p = VezCurrentCPU->ppMemWrite[ a >> VEZ_MEM_SHIFT ];
if ( p )
*(p + a) = d;
else
VezCurrentCPU->WriteHandler(a, d);
}

void VezWriteByte(UINT32 a, UINT8 d)
{
bprintf (PRINT_NORMAL, _T("VezWriteByte %d\n"), a);
a &= 0xFFFFF;

UINT8 * p = VezCurrentCPU->ppMemWrite[ a >> VEZ_MEM_SHIFT ];
if ( p )
*(p + a) = d;
else
VezCurrentCPU->WriteHandler(a, d);
}

void VezWriteWord(UINT32 a, UINT16 d)
{
bprintf (PRINT_NORMAL, _T("VezWriteWord %d\n"), a);
a &= 0xFFFFF;

UINT16 * p = (UINT16*)VezCurrentCPU->ppMemWrite[ a >> VEZ_MEM_SHIFT ];
if ( p )
*(p + (a / 2)) = d;
else {
VezCurrentCPU->WriteHandler(a, d);
VezCurrentCPU->WriteHandler(a+1, d >> 8);
}
}

void VezWriteLong(UINT32 a, UINT32 d)
{
bprintf (PRINT_NORMAL, _T("VezWriteLong %d\n"), a);
a &= 0xFFFFF;

UINT32 * p = (UINT32*)VezCurrentCPU->ppMemWrite[ a >> VEZ_MEM_SHIFT ];
if ( p )
*(p + (a / 4)) = d;
else {
VezCurrentCPU->WriteHandler(a, d);
VezCurrentCPU->WriteHandler(a+1, d >> 8);
VezCurrentCPU->WriteHandler(a+2, d >> 16);
VezCurrentCPU->WriteHandler(a+3, d >> 24);

}
}
static void VezCheatWrite(UINT32 a, UINT8 d)
{
bprintf (PRINT_NORMAL, _T("VezCheatWrite %d\n"), a);
a &= 0xfffff;

UINT8 * p;

p = VezCurrentCPU->ppMemWrite[ a >> VEZ_MEM_SHIFT ];
if ( p ) *(p + a) = d;

p = VezCurrentCPU->ppMemRead[ a >> VEZ_MEM_SHIFT ];
if ( p ) *(p + a) = d;

p = VezCurrentCPU->ppMemFetch[ a >> VEZ_MEM_SHIFT ];
if ( p ) *(p + a) = d;

p = VezCurrentCPU->ppMemFetchData[ a >> VEZ_MEM_SHIFT ];
if ( p ) *(p + a) = d;

VezCurrentCPU->WriteHandler(a, d);
}
From my outputs, i confirm the "a" argument is already wrong on arm.
So the issue seems to be at the call of those functions in either src/cpu/nec/v25sfr.c or src/cpu/nec/nec.cpp

Offline dink

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Re: Need some help with my libretro port
« Reply #94 on: October 13, 2016, 08:28:27 AM »
ahh, yes, the a, a+1,a+2 etc will never work on arm without le2be (or the other way around).  I think the reason some nec-v games work and not others is that the ones that work are only 8bit all-around.  (maybe, its just a theory).  On the other hand, I wonder how the other processors deal with that.  hrmm. 
(I'll post some better/more helpfull info when I can think of it!)

best regards,
- dink

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #95 on: October 13, 2016, 02:39:51 PM »
ahh, yes, the a, a+1,a+2 etc will never work on arm without le2be (or the other way around).
the raspberry cpu is little endian, same as x86.
I've gone a little further in my tests through bprint : it looks to me like "DefaultBase(Seg)" returns different results from the same input on x86 and arm, i'll try to investigate further later today.

Offline dink

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Re: Need some help with my libretro port
« Reply #96 on: October 13, 2016, 05:47:48 PM »
the raspberry cpu is little endian, same as x86.
I've gone a little further in my tests through bprint : it looks to me like "DefaultBase(Seg)" returns different results from the same input on x86 and arm, i'll try to investigate further later today.

I'm a dummy for assuming that, oops :)

you're on the right track though, that's exactly how I'd debug it.

I just looked at nec_intf.cpp:
Code: [Select]
// Handlers
 #ifdef FASTCALL
UINT8 (__fastcall *ReadHandler)(UINT32 a);
void (__fastcall *WriteHandler)(UINT32 a, UINT8 d);
UINT8 (__fastcall *ReadPort)(UINT32 a);
void (__fastcall *WritePort)(UINT32 a, UINT8 d);
 #else
UINT8 (__cdecl *ReadHandler)(UINT32 a);
void (__cdecl *WriteHandler)(UINT32 a, UINT8 d);
UINT8 (__cdecl *ReadPort)(UINT32 a);
void (__cdecl *WritePort)(UINT32 a, UINT8 d);
 #endif

is __fastcall defined on your side?  if it isn't, try defining it in the makefile.  I know that the makefile.sdl defines __fastcall as "" (nothing), this is OK.  just make sure -DFASTCALL is in the c/g++ compiler lines somewhere and try.  (its just an idea)

best regards,
- dink

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #97 on: October 13, 2016, 07:18:38 PM »
I didn't have (but i have a "undef __fastcall" somewhere, same as sdl), when i try adding it, i have issues building the core :
Code: [Select]
src/cpu/m68k/m68kconf.h:222:25: erreur: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?M68KFetchByte?
 unsigned int __fastcall M68KFetchByte(unsigned int a);
                         ^
src/cpu/m68k/m68kconf.h:223:25: erreur: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?M68KFetchWord?
 unsigned int __fastcall M68KFetchWord(unsigned int a);
                         ^
src/cpu/m68k/m68kconf.h:224:25: erreur: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?M68KFetchLong?
 unsigned int __fastcall M68KFetchLong(unsigned int a);
                         ^
src/cpu/m68k/m68kconf.h:231:33: erreur: expected ?)? before ?*? token
 extern unsigned int (__fastcall *M68KReadByteDebug)(unsigned int);
                                 ^
src/cpu/m68k/m68kconf.h:232:33: erreur: expected ?)? before ?*? token
 extern unsigned int (__fastcall *M68KReadWordDebug)(unsigned int);
                                 ^
src/cpu/m68k/m68kconf.h:233:33: erreur: expected ?)? before ?*? token
 extern unsigned int (__fastcall *M68KReadLongDebug)(unsigned int);
                                 ^
src/cpu/m68k/m68kconf.h:235:25: erreur: expected ?)? before ?*? token
 extern void (__fastcall *M68KWriteByteDebug)(unsigned int, unsigned int);
                         ^
src/cpu/m68k/m68kconf.h:236:25: erreur: expected ?)? before ?*? token
 extern void (__fastcall *M68KWriteWordDebug)(unsigned int, unsigned int);
                         ^
src/cpu/m68k/m68kconf.h:237:25: erreur: expected ?)? before ?*? token
 extern void (__fastcall *M68KWriteLongDebug)(unsigned int, unsigned int);
                         ^
In file included from src/cpu/m68k/m68k.h:383:0,
                 from src/cpu/m68k/m68kcpu.h:29,
                 from src/cpu/m68k/m68kops.c:1:
src/cpu/m68k/m68kconf.h:222:25: erreur: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?M68KFetchByte?
 unsigned int __fastcall M68KFetchByte(unsigned int a);
                         ^
src/cpu/m68k/m68kconf.h:223:25: erreur: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?M68KFetchWord?
 unsigned int __fastcall M68KFetchWord(unsigned int a);
                         ^
src/cpu/m68k/m68kconf.h:224:25: erreur: expected ?=?, ?,?, ?;?, ?asm? or ?__attribute__? before ?M68KFetchLong?
 unsigned int __fastcall M68KFetchLong(unsigned int a);
                         ^
src/cpu/m68k/m68kconf.h:231:33: erreur: expected ?)? before ?*? token
 extern unsigned int (__fastcall *M68KReadByteDebug)(unsigned int);
                                 ^
src/cpu/m68k/m68kconf.h:232:33: erreur: expected ?)? before ?*? token
 extern unsigned int (__fastcall *M68KReadWordDebug)(unsigned int);
                                 ^
src/cpu/m68k/m68kconf.h:233:33: erreur: expected ?)? before ?*? token
 extern unsigned int (__fastcall *M68KReadLongDebug)(unsigned int);
                                 ^
src/cpu/m68k/m68kconf.h:235:25: erreur: expected ?)? before ?*? token
 extern void (__fastcall *M68KWriteByteDebug)(unsigned int, unsigned int);
                         ^
src/cpu/m68k/m68kconf.h:236:25: erreur: expected ?)? before ?*? token
 extern void (__fastcall *M68KWriteWordDebug)(unsigned int, unsigned int);
                         ^
src/cpu/m68k/m68kconf.h:237:25: erreur: expected ?)? before ?*? token
 extern void (__fastcall *M68KWriteLongDebug)(unsigned int, unsigned int);
Also, i noticed nec_state->sregs[0] always return 0 on arm (for rtype), while it is 16384 on x86
« Last Edit: October 13, 2016, 07:29:54 PM by barbudreadmon »

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #98 on: October 13, 2016, 07:38:47 PM »
I was able to fix the build, but same issue on arm : nec_state->sregs[0] return 0

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #99 on: October 14, 2016, 02:15:04 AM »
My C/C++ level is too poor to fully understand how this "nec_state->sregs[0]" is handled, i tried adding
Code: [Select]
bprintf (PRINT_NORMAL, _T("Test : %d\n"), nec_state->sregs[0]);after the nec_state_t *nec_state = blahblah in nec.cpp, to see if and when this value get filled on x86, but it seems i only get 0 on both arch. Any suggestion on what i should try to bprint ?

Edit : btw, since i'm able to build with FASTCALL either on or off, what should i use on the long term ? What's the difference ?
« Last Edit: October 14, 2016, 04:51:40 AM by barbudreadmon »

Offline dink

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Re: Need some help with my libretro port
« Reply #100 on: October 14, 2016, 08:51:16 AM »
Idea:

find this in necpriv.h:
typedef enum { DS1, PS, SS, DS0 } SREGS;
typedef enum { AW, CW, DW, BW, SP, BP, IX, IY } WREGS;

change it to:
Code: [Select]
typedef enum { DS1 = 0, PS = 1, SS = 2, DS0 = 3 } SREGS;
typedef enum { AW = 0, CW = 1, DW = 2, BW = 3, SP = 4, BP = 5, IX = 6, IY = 7 } WREGS;

For now, put it back to its non-fastcall state.  and/or whenever we get a lead (like above), try both ways :)

best regards,
- dink

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #101 on: October 14, 2016, 02:38:38 PM »
Sadly, it didn't change anything. "DefaultBase(Seg)" keep returning 0. Those enum are related to how nec_state->sregs is handled ?

I tried to get some explanation on what's the difference between cdecl and fastcall, and i think i understood. What i don't understand is what's the difference between "_fastcall" (present in konami asterix, xexex and gijoe) and "__fastcall", if there is any difference, is that a typo ?

Also, i don't know if it could help debugging, but i know for sure https://github.com/libretro/mame2003-libretro/tree/master/src/cpu/nec and https://github.com/libretro/mame2010-libretro/tree/master/src/emu/cpu/nec implementation of nec cpu works on arm.
« Last Edit: October 14, 2016, 03:04:41 PM by barbudreadmon »

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #102 on: October 15, 2016, 01:48:49 AM »
With the following code in necinstr.c :
Code: [Select]
OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); CLKR(15,15,7,15,11,5,2,EA);
switch (ModRM & 0x38) {
case 0x00: bprintf (PRINT_NORMAL, _T("op 0x8e : DS1 : %d : %d\n"), DS1, src); Sreg(DS1) = src; break; /* mov es,ew */
case 0x08: Sreg(PS) = src; break; /* mov cs,ew */
case 0x10: Sreg(SS) = src; break; /* mov ss,ew */
case 0x18: bprintf (PRINT_NORMAL, _T("op 0x8e : DS0 : %d : %d\n"), DS0, src); Sreg(DS0) = src; break; /* mov ds,ew */
// default:   logerror("%06x: MOV Sreg - Invalid register\n",PC(nec_state));
}
nec_state->no_interrupt=1;
}
I noticed the following outputs :
on X86 :
Code: [Select]
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 0
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 8192
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 12288
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 12288
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 57344
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 59392
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 51200
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 52224
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 52224
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 51200
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 8192
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 57344
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 16384
on ARM :
Code: [Select]
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 3
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
i notice nec_state->sregs[0] is depleting then the 0x00 case in 0x8e opcode will never run again, and nec_state->sregs[3] will start at 53248 and never change, unlike on x86.

Then i tried :
Code: [Select]
OP( 0x8e, i_mov_sregw ) { UINT16 src; GetModRM; src = GetRMWord(ModRM); bprintf(PRINT_NORMAL, _T("op 0x8e : ModRM : %d : %d\n"), ModRM, src); CLKR(15,15,7,15,11,5,2,EA);
switch (ModRM & 0x38) {
case 0x00: bprintf (PRINT_NORMAL, _T("op 0x8e : DS1 : %d : %d\n"), DS1, src); Sreg(DS1) = src; break; /* mov es,ew */
case 0x08: Sreg(PS) = src; break; /* mov cs,ew */
case 0x10: Sreg(SS) = src; break; /* mov ss,ew */
case 0x18: bprintf (PRINT_NORMAL, _T("op 0x8e : DS0 : %d : %d\n"), DS0, src); Sreg(DS0) = src; break; /* mov ds,ew */
// default:   logerror("%06x: MOV Sreg - Invalid register\n",PC(nec_state));
}
nec_state->no_interrupt=1;
}
And got the following outputs :
X86:
Code: [Select]
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 218 : 0
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 0
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 218 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 218 : 8192
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 8192
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 218 : 12288
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 12288
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 218 : 12288
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 12288
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 16384
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 57344
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 57344
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 59392
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 59392
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 49152
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 51200
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 51200
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 52224
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 52224
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 52224
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 52224
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 51200
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 51200
ARM :
Code: [Select]
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 55296
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 4096
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 192 : 3
RetroArch [libretro DEBUG] :: op 0x8e : DS1 : 0 : 3
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : DS0 : 3 : 53248
RetroArch [libretro DEBUG] :: op 0x8e : ModRM : 216 : 53248
Those numbers on arm feels quite strange, do you think i'm on the right track ? Next step would be to check Wreg values ?
« Last Edit: October 15, 2016, 02:03:02 AM by barbudreadmon »

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #103 on: October 15, 2016, 02:30:00 AM »
ModRM never returning anything else than 216 or 192 on arm means Mod_RM.RM.w[ModRM] will never return anything except 0, which means only Wreg(0) is returned as GetRMWord(ModRM) on arm, unlike on x86 where it will use various Wreg(x) because values like 218, 193 or 194 are sometimes returned by ModRM. Sounds like a good culprit ?

Offline barbudreadmon

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Re: Need some help with my libretro port
« Reply #104 on: October 15, 2016, 04:09:10 AM »
I went from getModRM to FETCH(), then to cpu_readop_arg, then to cpu_readmem20_arg, there i used the following code :
Code: [Select]
UINT8 cpu_readmem20_arg(UINT32 a)
{
a &= 0xFFFFF;

UINT8 * p = VezCurrentCPU->ppMemFetchData[ a >> VEZ_MEM_SHIFT ];
if ( p ) {
bprintf (PRINT_NORMAL, _T("cpu_readmem20_arg first a: %d, p: %d, result: %d\n"), a, p, *(p + a));
return *(p + a);
}
else {
bprintf (PRINT_NORMAL, _T("cpu_readmem20_arg second a: %d\n"), a, p, *(p + a));
return VezCurrentCPU->ReadHandler(a);
}
}
And noticed something interesting : both arch have the same "a" and "result" for the first 7 call of this function :
Code: [Select]
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 1048561, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 1048562, p: 1915506696, result: 8
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 1048563, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 1048564, p: 1915506696, result: 63
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260098, p: 1915506696, result: 255
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260099, p: 1915506696, result: 255
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260101, p: 1915506696, result: 254
Then on X86, every call after the 7th stays the same as the 7th, while on arm, it goes like this :
Code: [Select]
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260357, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260358, p: 1915506696, result: 128
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260360, p: 1915506696, result: 66
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260361, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260429, p: 1915506696, result: 209
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260431, p: 1915506696, result: 1
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260433, p: 1915506696, result: 255
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260437, p: 1915506696, result: 202
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260439, p: 1915506696, result: 255
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260443, p: 1915506696, result: 3
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260445, p: 1915506696, result: 123
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260446, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260571, p: 1915506696, result: 211
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260573, p: 1915506696, result: 17
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260574, p: 1915506696, result: 235
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260576, p: 1915506696, result: 5
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260577, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260584, p: 1915506696, result: 0
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260585, p: 1915506696, result: 208
RetroArch [libretro DEBUG] :: cpu_readmem20_arg first a: 260587, p: 1915506696, result: 192
"a" keeps increasing, leading to different results, which would mean "(Sreg(PS)<<4) + sChipsPtr->ip++" return wrong values on arm after this 7th call.

Also, i already tried replacing FETCH()/FETCHWORD() macro by :
Code: [Select]
#define FETCH() fetch(nec_state)
#define FETCHWORD() fetchword(nec_state)
as in the mame2010 nec sources i linked, it didn't change the results

I'll stop my investigation for now, i hope all those data will give you some idea, and thanks for helping me :)

Edit : By the way, my reference game for those tests is always rtype, but for this last test i confirm the same is happening with mrheli.
Edit2 : i did one last test by replacing FETCH() macro by
Code: [Select]
#define FETCH() ({ UINT8 retval; retval = cpu_readop_arg((Sreg(PS)<<4) + sChipsPtr->ip); bprintf (PRINT_NORMAL, _T("test %d, %d, %d\n"), Sreg(PS)<<4, sChipsPtr->ip, retval); sChipsPtr->ip++; retval; })Seems like "Sreg(PS)<<4" result is fine, but "sChipsPtr->ip" is not (keep increasing on arm while it stays the same on x86).
« Last Edit: October 15, 2016, 05:07:10 AM by barbudreadmon »